1. Field of the Invention
This invention relates to a semiconductor device and a method for making the same, more particularly to a semiconductor device and a method involving formation of diffusion buried bit lines in a base of a substrate.
2. Description of the Related Art
Dynamic random access memory (DRAM) device is a volatile memory device for storing data or information, and includes an array of transistors and capacitors, bit lines electrically coupled to sources or drains of the transistors, and word lines electrically coupled to gates of the transistors. Development of the DRAM devices in the DRAM industry has been focused on how to increase the storage capacity thereof. One way of increasing the storage capacity is accomplished by forming deep trenches in a Si substrate and buried bit lines in side walls of the trenches. The smaller the width of the trenches, the higher will be the storage capacity. However, to reduce the width of the trenches from the current DRAM generation (the width of the trench being about 60 nm) to the next DRAM generation (the width of the trench being about 20-40 nm) can be a great challenge.
FIGS. 1A to 1F illustrate consecutive steps of a conventional method of forming buried bit lines inside walls of trenches in a semiconductor substrate for ma king a vertical transistor DRAM device. Each of the buried bit lines is adapted to be electrically coupled to a source or a drain of a transistor formed in the semiconductor substrate. The method includes: forming a patterned hard mask 93 on a semiconductor substrate 92 so that the substrate 92 has predetermined regions 922 not covered by the patterned hard mask 93 (see FIG. 1A); etching the substrate 92 at the predetermined regions 922 not covered by the hard mask 93 so as to form a plurality of trenches 94 in the substrate 92 (see FIG. 1B); forming a liner layer 95 on trench side walls 941 and a bottom wall 942 of each of the trenches 94 (see FIG. 1C); removing a bottom of the liner layer 95 to uncover the bottom wall 942 of each trench 94 by dry etching (see FIG. 1D); ion implanting a dopant into the substrate 92 at the bottom wall 942 of each trench 94 by ion implantation techniques so as to form a doped region 96 at the bottom wall 942 of each trench 94 (see FIG. 1E); and deepening each of the trenches 94 by dry etching in order to cut the doped region 96 into two separate halves that form two separated buried bit lines 961 in the trench side walls 941 of each trench 94, respectively (see FIG. 1F).
The conventional method is disadvantageous in that the liner layer 95 is required to have a thickness (at least 10 nm thick) sufficient to prevent scattering of implantation ions or dopant into the trench side walls 941 of the trenches 94. As such, the liner layer 95 considerably reduces the space of each trench 94 available for ion implantation and for trench deepening, which results in difficulty in performing the ion implantation and the trench deepening. In addition, since the doped region 96 thus formed is relatively thick in the depth direction, each trench 94 is required to be deepened an extra depth (e.g., about 200 nm) that is greater than the thickness of the doped region 96 in the depth direction so as ensure the doped region 96 is cut through to form the two separated buried bit lines 961. The extra deepening of each trench 94 is very difficult to perform in view of a narrow space in the trench 94.